The present invention relates, generally, to methods and structures for improving the reliability and manufacturability of multilevel interconnects in integrated circuits and, more particularly, to a dual damascene process with barrier enhancement at the via sidewalls and improved capability for fabricating high aspect ratio interconnect structures.
Through advanced semiconductor processing techniques, integrated circuit devices with sub-micron and sub-half-micron features sizes can now be manufactured. This trend toward deep submicron technology (i.e., involving feature sizes less than 0.35 microns) has, in turn, driven the need for multilayer interconnects. As a result, circuit performance in the deep submicron regime is increasingly a function of the delay time of electronic signals traveling between the millions of gates and transistors present on the typical integrated circuit chip. Parasitic capacitance and resistance effects resulting from these otherwise passive interconnect structures must therefore be well-controlled. Toward this end, recent trends emphasize the use of low resistance metals (e.g., copper) in conjunction with insulating materials with low dielectric constants (xe2x80x9clow-k dielectricsxe2x80x9d) between metal lines. A low-k dielectric is a dielectric material which exhibits a dielectric constant substantially less than conventional dielectric materials such as silicon dioxide, silicon nitride, and silicon oxynitride. Silicon dioxide, for example, has a dielectric constant of about 4.0. Copper is desirable in that its conductivity is relatively high and it is less susceptible to electromigration failure than many metals (for example, aluminum).
Modern semiconductor processing techniques increasingly employ Chemical-Mechanical Polishing (CMP) in the fabrication of interconnect layers, particularly where the number of layers rises above three and the conductive lines themselves are characterized by a high aspect ratio (e.g., lines on the order of 0.25 xcexcm in width and on the order of 1.0 xcexcm in height). In a paradigmatic CMP process, a resinous polishing pad (e.g., a polyurethane pad) is employed in conjunction with a mechanically and chemically active slurry. When pressure is applied between the polishing pad and the wafer being polished, mechanical stresses are concentrated on the exposed edges of the adjoining cells in the cellular pad. Abrasive particles within the slurry concentrated on these edges tend to create zones of localized stress at the workpiece in the vicinity of the exposed edges of the polishing pad. This localized pressure creates mechanical strain on the chemical bonds comprising the surface being polished, rendering the chemical bonds more susceptible to chemical attack by the slurry. Thus, with the correct choice of slurry, pressure, and other process conditions, a highly planar surface may be formed on the wafer.
A fabrication method which employs CMP techniques and which addresses many of the above concerns is the so-called xe2x80x9cdamascenexe2x80x9d process. Damascening acquired its name from an ornamental technique, generally attributed to metal-workers in ancient Damascus, which involved scribing or incising patterns into steel (most often swords) then filling the resulting grooves with gold or silver prior to final polish. Similarly, the modern semiconductor analog of this process involves, in the broadest sense, forming patterns in a dielectric layer, filling the resulting pattern with interconnect metal, then polishing away the excess metal on the wafer surface and leaving inlaid interconnect metal features.
There are two major classes of damascene processes: single-damascene and dual-damascene. These two processes are illustrated in highly simplified form in FIGS. 1A and 1B (details of the various intermediary steps are discussed in further detail below). Briefly, and with reference to FIG. 1A, a single damascene process involves making contact to a lower level conductor 102 (formed, for example, on substrate 107) by patterning dielectric layer 106 and forming a conductive plug 104 in dielectric layer 106, then patterning a second dielectric layer 110 and forming the actual interconnect wiring metallization 108 in patterned dielectric layer 110. In a dual-damascene process (FIG. 1B), the interconnect wiring 108 and plug 104 are formed by patterning both the via and the trench patterns into dielectric 106, then filling them simultaneously with metal. The dual damascene process offers the advantages of process simplification and lower manufacturing cost.
The use of Cu as interconnect metal in dual damascene IC devices gives rise to many difficulties and challenges. For example, copper tends to migrate or diffuse into the silicon dioxide, where it acts to increase leakage currents or actually short-out adjacent conductors. In addition, once Cu diffuses through the silicon dioxide and reaches the silicon devices, the device will generally malfunction in some manner. This has motivated the semiconductor industry to form diffusion barriers around any copper conductors present in the structure. The inner surfaces (i.e., the bottom and sides of the via and trench) are typically coated with a thin layer of Ti, TiN, Ta, TaN, WN or another adequate barrier metal.
TiN, which is popular as a barrier layer in Al/W interconnect structures, is generally unsatisfactory for use with advanced copper interconnect structures. First, it has been found that TiN exhibits inferior resistance to copper migration. Second, TiN is not compatible with current Cu plating techniques used in Cu deposition due to, among other things, problems with adhesion of the Cu to TiN. Specifically, Cu is plated directly on TiN along the wafer edge with poor adhesion.
As a result, the use of Ta and/or TaN as a barrier metal has become quite popular. Ta and TaN may be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). Unfortunately, however, CVD TaN/Ta suffers from low deposition rate and high deposition temperature (i.e., temperatures greater than 500xc2x0 C.). These high temperatures and low deposition rates are incompatible with current interconnect processes as well as future processes incorporating low-k dielectrics. Even in the case where an ionized PVD process is used, high aspect ratio interconnects are prone to poor step coverage of the barrier layer at the sidewall of the vias. More particularly, referring now to FIG. 2A, a via structure 104 formed within a dielectric 106 (linking metal pattern 108 and lower level conductor 102), is lined with a barrier 224. As mentioned above, barrier 224 typically comprises Ta or TaN. Using known methods, for example, ionized PVD, the thickness of barrier layer 224 is significantly less near the lower portion of the via sidewall (226). As a result, these regions are particularly susceptible to Cu migration (228).
Furthermore, referring now to FIG. 2B, in the case where conductor 102 comprises copper, a layer of copper 230 may be deposited along the sidewalls near the bottom of the via prior to formation of metal barrier 224. That is, copper (from copper conductor 102) tends to be sputtered along the sidewalls (1) during the silicon nitride etch used to open the via connection to conductor 102; and (2) during the sputter-clean of conductor 102 just prior to deposition of metal barrier 224. As mentioned above, this copper may then diffuse into surrounding structures, leading to significant reliability problems.
In addition, etching of high aspect ratio (AR) dual-damascene features is itself very challenging. Although etching dielectrics is generally easier than etching metals (thus the desirability of damascene processes), as the lateral feature size of interconnects continue to shrink, etching the dual damascene structures of very high AR features leads to fabrication difficulties.
Methods and structures are therefore needed in order to overcome these and other limitations in the prior art. More particularly, there is a long felt need for reliable and manufacturable interconnect structures.
An interconnect fabrication process and structure in accordance with the present invention overcomes limitations of the prior art by providing barrier enhancement at the via sidewalls and easing the fabrication of high aspect ratio dual-damascene interconnect structures. In accordance with the present invention, a via structure is patterned into the via dielectric first. A dielectric barrier (for example, anisotropically etched silicon nitride) is formed only along the via sidewalls in the dual damascene structure prior to deposition of a metal barrier (for example, Ta/TaN). In this way, the effective barrier thickness along the bottom of the via sidewalls is increased, eliminating the structure""s susceptibility to metal migration. The absence of dielectric barrier along the interconnect trench sidewalls leads to low interconnect resistance and low interconnect capacitance. The present invention also provides an improved fabrication method for obtaining high aspect ratio dual damascene interconnect structures.